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#LyX 1.6.5 created this file. For more info see http://www.lyx.org/
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\lyxformat 276
\begin_document
\begin_header
\textclass literate-article
\begin_preamble
\usepackage[dvips,colorlinks=true,linkcolor=blue]{hyperref}
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\DeclareGraphicsExtensions{.pdf}
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\end_preamble
\language american
\inputencoding auto
\font_roman ae
\font_sans default
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\font_sf_scale 100
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\graphics default
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\spacing single
\papersize a4paper
\use_geometry true
\use_amsmath 1
\use_esint 0
\cite_engine basic
\use_bibtopic false
\paperorientation portrait
\leftmargin 36pt
\topmargin 1in
\rightmargin 36pt
\bottommargin 1in
\secnumdepth 3
\tocdepth 3
\paragraph_separation indent
\defskip medskip
\quotes_language english
\papercolumns 2
\papersides 1
\paperpagestyle fancy
\tracking_changes false
\output_changes false
\author ""
\author ""
\end_header

\begin_body

\begin_layout Title
b16 Documentation
\end_layout

\begin_layout Author

\noun on
Bernd Paysan
\end_layout

\begin_layout Standard
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
lhead{
\end_layout

\end_inset

b16 Documentation
\begin_inset ERT
status collapsed

\begin_layout Standard

}
\backslash
chead{
\end_layout

\end_inset


\noun on
Bernd Paysan
\noun default

\begin_inset ERT
status collapsed

\begin_layout Standard

}
\end_layout

\end_inset


\end_layout

\begin_layout Abstract
This article presents architecture and implementation of the b16 stack processor.
 This processor is inspired by 
\noun on
Chuck Moore'
\noun default
s newest Forth processors.
 The minimalistic design fits into small FPGAs and ASICs and is ideally
 suited for applications that need both control and calculations.
 The factor is shifted towards control to save space.
 The synthesizible implementation uses Verilog.
\end_layout

\begin_layout Section*
Introduction
\end_layout

\begin_layout Standard
Minimalistic CPUs can be used in many designs.
 A state machine often is too complicated and too difficult to develop,
 when there are more than a few states.
 A program with subroutines can perform a lot more complex tasks, and is
 easier to develop at the same time.
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 Also, ROM and RAM blocks occupy much less place on silicon than 
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\begin_inset Quotes eld
\end_inset

random logic
\begin_inset Quotes erd
\end_inset

.
 That's also valid for FPGAs, where 
\begin_inset Quotes eld
\end_inset

block RAM
\begin_inset Quotes erd
\end_inset

 is---in contrast to logic elements---plenty.
\end_layout

\begin_layout Standard
The architecture is inspired by the c18 from
\noun on
 Chuck Moore
\noun default
 
\begin_inset LatexCommand cite
key "c18"

\end_inset

.
 The exact instruction mix is different; it also differs from the standard
 b16 core.
 Also, this architecture is byte-addressed.
\end_layout

\begin_layout Standard
A word about Verilog: Verilog is a C-like language, but tailored for the
 purpose to simulate logic, and to write synthesizible code.
 Variables are bits and bit vectors, and assignments are typically non-blocking,
 i.e.
 on assignments first all right sides are computed, and the left sides are
 modified afterwards.
 Also, Verilog has events, like changing of values or clock edges, and blocks
 can wait on them.
\end_layout

\begin_layout Section
Architectural Overview
\end_layout

\begin_layout Standard
The core components are
\end_layout

\begin_layout Itemize
An ALU
\end_layout

\begin_layout Itemize
A data stack with top and next of stack (T and N) as inputs for the ALU
\end_layout

\begin_layout Itemize
A return stack
\end_layout

\begin_layout Itemize
An instruction pointer P 
\end_layout

\begin_layout Itemize
An address mux 
\family typewriter
addr
\family default
, to address external memory
\end_layout

\begin_layout Itemize
An instruction latch I
\end_layout

\begin_layout Standard
Figure 
\begin_inset LatexCommand ref
reference "blockdiagram"

\end_inset

 shows a block diagram.
\end_layout

\begin_layout Standard
\begin_inset Float figure
wide false
sideways false
status open

\begin_layout Standard
\align center
\begin_inset Graphics
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    filename b16-small.pdf
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    width 100col%

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Caption

\begin_layout Standard
Block Diagram
\begin_inset LatexCommand label
name "blockdiagram"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


\end_layout

\begin_layout Subsection
Register
\end_layout

\begin_layout Standard
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In addition to the standard Forth machine registers there are control registers
 for external RAM (
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\family typewriter
rd
\family default
 and 
\family typewriter
wr
\family default
), stack pointers (
\family typewriter
sp
\family default
 and 
\family typewriter
rp
\family default
), and a carry 
\family typewriter
c
\family default
.
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 For consistency with Chuck Moores' nomenclature, violating most coding
 style guidelines, the Forth machine registers are single-letter variables
 in upper case.
 Since the source code is a LyX document, you can use the 
\begin_inset Quotes eld
\end_inset

search whole word
\begin_inset Quotes erd
\end_inset

 mode to find them easily, and they also show up on top of the signal list
 during simulation.
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\end_layout

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\end_inset


\end_layout

\begin_layout Standard
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="9" columns="2">
<features>
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\begin_inset Text

\begin_layout Standard
T
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
Top of Stack
\end_layout

\end_inset
</cell>
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\begin_inset Text

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I
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P
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\begin_inset Text

\begin_layout Standard
Program Counter
\end_layout

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</cell>
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\begin_inset Text

\begin_layout Standard
R
\end_layout

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Top of Returnstack
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state
\end_layout

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\begin_layout Standard
Processor State
\end_layout

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sp
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\begin_inset Text

\begin_layout Standard
Stack Pointer
\end_layout

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</cell>
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<row topline="true" bottomline="false">
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
rp
\end_layout

\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
Return Stack Pointer
\end_layout

\end_inset
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\begin_layout Standard
c
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\end_inset
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<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
Carry Flag
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Standard
\begin_inset VSpace medskip
\end_inset


\end_layout

\begin_layout Scrap
<<register declarations>>=
\newline

reg [sdep-1:0] sp;
\newline

reg [rdep-1:0] rp;
\newline


\newline

reg `L T, I, P, R;
\newline

reg [1:0] state;
\newline

reg c;
\newline

@
\end_layout

\begin_layout Standard
\begin_inset Float table
wide true
sideways false
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jz
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jnc
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for slot 3 
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\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
+c
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
\begin_inset Formula $*+$
\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
\begin_inset Formula $/-$
\end_inset


\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard

\end_layout

\end_inset
</cell>
</row>
<row topline="false" bottomline="false">
<cell alignment="center" valignment="top" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
10 
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
!+
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
@+
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
@
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
lit
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
c!+
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
c@+
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
c@
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
litc
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard

\end_layout

\end_inset
</cell>
</row>
<row topline="false" bottomline="true">
<cell alignment="center" valignment="top" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
!.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
@.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
@
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
lit
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
c!.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
c@.
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
c@
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
litc
\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard

\emph on
for slot 1
\emph default
 
\end_layout

\end_inset
</cell>
</row>
<row topline="false" bottomline="true">
<cell alignment="center" valignment="top" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
18 
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
nip
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
drop
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
over
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
dup
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
>r
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard

\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
r>
\end_layout

\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard

\end_layout

\end_inset
</cell>
<cell alignment="left" valignment="top" bottomline="true" rightline="true" usebox="none">
\begin_inset Text

\begin_layout Standard
 
\end_layout

\end_inset
</cell>
</row>
</lyxtabular>

\end_inset


\end_layout

\begin_layout Standard
\begin_inset Caption

\begin_layout Standard
Instruction Set
\begin_inset LatexCommand label
name "instructions"

\end_inset


\end_layout

\end_inset


\end_layout

\end_inset


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\end_layout

\begin_layout Section
Instruction Set
\end_layout
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\begin_layout Standard
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There are 32 different instructions.
 Since several instructions fit into a 16 bit word, we call the bits to
 store the packed instructions in an instruction word 
\begin_inset Quotes eld
\end_inset

slot
\begin_inset Quotes erd
\end_inset
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, and the instruction word itself 
\begin_inset Quotes eld
\end_inset
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bundle
\begin_inset Quotes erd
\end_inset

.
 The arrangement here is 1,5,5,5, i.e.
 the first slot is only one bit large (the more significant bits are filled
 with 0), and the others all 5 bits.
\end_layout

\begin_layout Standard
The operations in one instruction word are executed one after the other.
 Each instruction takes one cycle, memory operation (including instruction
 fetch) need another cycle.
 Which instruction is to be executed is stored in the variable 
\family typewriter
state
\family default
.
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\end_layout

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\begin_layout Standard
The instruction set is divided into four groups: jumps, ALU, memory, and
 stack.
 Table 
\begin_inset LatexCommand ref
reference "instructions"

\end_inset

 shows an overview over the instruction set.
 Note: Some special characters indicate functions as follows:
\end_layout

\begin_layout Description
! 
\begin_inset Quotes eld
\end_inset

store
\begin_inset Quotes erd
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\end_inset


\end_layout

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\begin_layout Description
@ 
\begin_inset Quotes eld
\end_inset

load
\begin_inset Quotes erd
\end_inset

, 
\end_layout

\begin_layout Description
> 
\begin_inset Quotes eld
\end_inset

to
\begin_inset Quotes erd
\end_inset

 if before, 
\begin_inset Quotes eld
\end_inset

from
\begin_inset Quotes erd
\end_inset

 if afterwards.
\end_layout

\begin_layout Standard
Operations will be described using a 
\begin_inset Quotes eld
\end_inset

stack effect
\begin_inset Quotes erd
\end_inset

.
 This is a template for the stack elements before and after the operation,
 separated by a long dash.
 The names are listed in the order bottom to top, unchanged stack elements
 below are not listed.
\end_layout

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\begin_layout Standard
Jumps use the rest of the instruction word as target address (except 
\family typewriter
ret
\family default
).
 The lower bits of the instruction pointer P are replaced, there's nothing
 added.
 For instructions in the last slot, no address remains, so they use T (TOS)
 as target.
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Scrap
<<instruction selection>>=
\newline

// instruction and branch target selection   
\newline

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wire [4:0] inst, rwinst;
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\newline

reg `L jmp;
\newline


\newline

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assign inst = { 4'b0000, data[15], I[14:0] }
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\newline

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              >> (5*(3-state[1:0]));
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\newline

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assign rwinst = { 5'b00000, I[14:0] }
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\newline

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                >> (5*(3-state[1:0]));
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\newline


\newline

always @(state or I or P or T or data)
\newline

   case(state[1:0])
\newline

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     2'b00: jmp = { data[14:0], 1'b0 };
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\newline

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     2'b01: jmp = { P[15:11], I[9:0], 1'b0 };
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\newline

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     2'b10: jmp = { P[15:6], I[4:0], 1'b0 };
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\newline

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     2'b11: jmp = { T[15:1], 1'b0 };
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\newline

   endcase // casez(state)
\newline

@
\end_layout

\begin_layout Standard
The instructions themselves are executed depending on 
\family typewriter
inst
\family default
:
\end_layout

\begin_layout Scrap
<<instructions>>=
\newline

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case(inst)
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\newline

   <<control flow>>
\newline

   <<ALU operations>>
\newline

   <<load/store>>
\newline

   <<stack operations>>
\newline

endcase // case(inst)
\newline

@
\end_layout

\begin_layout Subsection
Jumps
\end_layout

\begin_layout Standard
In detail, jumps are performed as follows: the target address is stored
 in the address latch 
\family typewriter
addr
\family default
, which addresses memory, not in the P register.
 The register P will be set to the incremented value of 
\family typewriter
addr
\family default
, after the instruction fetch cycle.
 Apart from 
\family typewriter
call
\family default
, 
\family typewriter
jmp
\family default
 and 
\family typewriter
ret
\family default
 there are conditional jumps, which test for 0 and carry.
 The lowest bit of the return stack is used to save the carry flag across
 calls.
 Conditional instructions don't consume the tested value, which is different
 from Forth.
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Standard
To make it easier to understand, I also define the effect of an instruction
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 in a pseudo language.
 Every instruction has a stack effect (before---after) with top of stack
 on the right, 
\begin_inset Quotes eld
\end_inset

r:
\begin_inset Quotes erd
\end_inset

 prefix indicating return stack, and register assignments:
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\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
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nop ( --- )
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\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
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call ( ---r:P ) 
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\begin_inset Formula $\mathrm{P}\leftarrow jmp$
\end_inset

; 
\begin_inset Formula $\mathrm{c}\leftarrow0$
\end_inset

 
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
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jmp ( --- ) 
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\begin_inset Formula $\mathrm{P}\leftarrow jmp$
\end_inset


\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
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ret ( r:a--- ) 
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\begin_inset Formula $\mathrm{P}\leftarrow a\wedge\$\mathrm{FFFE}$
\end_inset

; 
\begin_inset Formula $\mathrm{c}\leftarrow a\wedge1$
\end_inset

 
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
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jz ( n--- ) 
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\begin_inset Formula $\mathbf{if}(n=0)\,\mathrm{P}\leftarrow jmp$
\end_inset

 
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
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jnz ( n--- ) 
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\begin_inset Formula $\mathbf{if}(n\ne0)\,\mathrm{P}\leftarrow jmp$
\end_inset

 
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
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jc ( x--- ) 
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\begin_inset Formula $\mathbf{if}(c)\,\mathrm{P}\leftarrow jmp$
\end_inset

 
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
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jnc ( x--- ) 
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\begin_inset Formula $\mathbf{if}(c=0)\,\mathrm{P}\leftarrow jmp$
\end_inset

 
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Scrap
<<control flow>>=
\newline

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5'b00001: begin // call
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\newline

   rp <= rpdec;
\newline

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   R <= { ~|state ? incaddr[15:1] : P[15:1], c };
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\newline

   P <= jmp;
\newline

   c <= 1'b0;
\newline

   if(state == 2'b11) `DROP;
\newline

end // case: 5'b00001
\newline

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5'b00010: begin // jmp
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\newline

   P <= jmp;
\newline

   if(state == 2'b11) `DROP;
\newline

end
\newline

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5'b00011: // ret
\newline

          { rp, c, P, R } <= 
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\newline

          { rpinc, R[0], R[l-1:1], 1'b0, toR };
\newline

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5'b00100, 5'b00101, 5'b00110, 5'b00111:
\newline

begin // conditional jmps
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\newline

   if((inst[1] ? c : zero) ^ inst[0]) 
\newline

      P <= jmp;
\newline

   `DROP;
\newline

end
\newline

@
\end_layout

\begin_layout Subsection
ALU Operations
\end_layout

\begin_layout Standard
The ALU instructions use the ALU, which computes a result 
\family typewriter
res
\family default
 and a carry bit from T and N.
 The instruction 
\family typewriter
com
\family default
 is an exception, since it only inverts T---that doesn't require an ALU.
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Standard
Ordinary ALU instructions just write the result of the ALU into T and c,
 and reload N.
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
xor ( a b---r ) 
\begin_inset Formula $r\leftarrow a\oplus b$
\end_inset


\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
com ( a---r ) 
\begin_inset Formula $r\leftarrow a\oplus\$\mathrm{FFFF}$
\end_inset

, 
\begin_inset Formula $\mathrm{c}\leftarrow1$
\end_inset


\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
and ( a b---r ) 
\begin_inset Formula $r\leftarrow a\wedge b$
\end_inset


\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
or ( a b---r ) 
\begin_inset Formula $r\leftarrow a\vee b$
\end_inset


\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
+ ( a b---r ) 
\begin_inset Formula $\mathrm{c},r\leftarrow a+b$
\end_inset


\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
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+c ( a b---r ) 
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\begin_inset Formula $\mathrm{c},r\leftarrow a+b+\mathrm{c}$
\end_inset


\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
\begin_inset Formula $*$
\end_inset

+ ( a b---a r ) 
\begin_inset Formula $\mathbf{if}(\mathrm{c})\, c_{n},r\leftarrow a+b\,\mathbf{else}\, c_{n},r\leftarrow0,b$
\end_inset

; 
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\begin_inset Formula $r,\mathrm{R},\mathrm{c}\leftarrow c_{n},r,\mathrm{R}$
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\end_inset


\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
/-- ( a b---a r ) 
\begin_inset Formula $c_{n},r_{n}\leftarrow a+b+1;$
\end_inset

 
\begin_inset Formula $\mathbf{if}(\mathrm{c}\vee c_{n})\, r\leftarrow r_{n}$
\end_inset

; 
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\begin_inset Formula $\mathrm{c},r,\mathrm{R}\leftarrow r,\mathrm{R},\mathrm{c}\vee c_{n}$
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\end_inset

 
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Scrap
<<ALU operations>>=
\newline

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5'b01001: // com
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\newline

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   { c, T } <= { 1'b1, ~T };
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\newline

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5'b01110: // *+
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\newline

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   { T, R, c } <=
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\newline

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   { c ? { carry, res } : { 1'b0, T }, R };
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\newline

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5'b01111: // /-
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\newline

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   { c, T, R } <=
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\newline

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   { (c | carry) ? res : T, R, (c | carry) };
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\newline

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5'b01000, 5'b01010, 5'b01011, 5'b01100, 5'b01101:
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\newline

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   // xor, and, or, +, +c
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\newline

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   { sp, c, T } <= { spinc, carry, res };
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\newline

@
\end_layout

\begin_layout Subsection
Memory Instructions
\end_layout

\begin_layout Standard
Memory instructions use either T as address, and N as data (source or destinatio
n), or P as address, and T as destination (literals).
 The address is auto-incremented, except for instructions in the first slot
 which use T as address---this is to implement read-modify-write instructions
 (non-incremeting is written as @.
 or !.
 in the assembler, don't care as @* or !*).
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
!+ ( n A---A' ) 
\begin_inset Formula $mem[A]\leftarrow n$
\end_inset

; 
\begin_inset Formula $\mathrm{A'}\leftarrow\mathrm{A}+2$
\end_inset


\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
@+ ( A---n A' ) 
\begin_inset Formula $n\leftarrow mem[\mathrm{A}]$
\end_inset

; 
\begin_inset Formula $\mathrm{A'}\leftarrow\mathrm{A}+2$
\end_inset


\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
@ ( A---n ) 
\begin_inset Formula $n\leftarrow mem[\mathrm{A}]$
\end_inset

; 
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
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lit ( ---n ) 
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\begin_inset Formula $n\leftarrow mem[\mathrm{P}]$
\end_inset

; 
\begin_inset Formula $\mathrm{P}\leftarrow\mathrm{P}+2$
\end_inset


\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
c!+ ( c A---A' ) 
\begin_inset Formula $mem.b[\mathrm{A}]\leftarrow c$
\end_inset

; 
\begin_inset Formula $\mathrm{A'}\leftarrow\mathrm{A}+1$
\end_inset


\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
c@+ ( A---c A' ) 
\begin_inset Formula $c\leftarrow mem.b[\mathrm{A}]$
\end_inset

; 
\begin_inset Formula $\mathrm{A'}\leftarrow\mathrm{A}+1$
\end_inset


\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
c@ ( A---c ) 
\begin_inset Formula $c\leftarrow mem.b[\mathrm{A}]$
\end_inset

; 
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
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litc ( ---c ) 
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\begin_inset Formula $c\leftarrow mem.b[\mathrm{P}]$
\end_inset

; 
\begin_inset Formula $\mathrm{P}\leftarrow\mathrm{P}+1$
\end_inset


\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Scrap
<<address handling>>=
\newline

wire `L incaddr, dataw, datas;
\newline

wire tos2r, tos2n;
\newline

wire incby, bswap, addrsel, access, rd;
\newline

wire [1:0] wr;
\newline


\newline

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assign incby = (rwinst[4:2] != 3'b101);
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\newline

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assign access = (rwinst[4:3]==2'b10);
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\newline

assign addrsel = rd ? 
\newline

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      (access & (rwinst[1:0] != 2'b11)) : |wr;
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\newline

assign rd = (state==2'b00) || 
\newline

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            (access && (rwinst[1:0]!=2'b00));
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\newline

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assign wr = (access && (rwinst[1:0]==2'b00)) ?
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\newline

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            { ~rwinst[2] | ~T[0], 
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\newline

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              ~rwinst[2] | T[0] } : 2'b00;
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\newline

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assign addr = addrsel ? T : P;
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\newline

assign incaddr = addr + incby + 1;
\newline

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assign tos2n = (!rd | (rwinst[1:0] == 2'b11));
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\newline

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assign toN = tos2n ? T : dataw;
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\newline

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assign bswap = ~incby ^ addr[0];
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\newline

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assign datas = bswap ? { data[7:0], data[l-1:8] }
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\newline

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                     : data;
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\newline

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assign dataw = incby ? datas
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\newline

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                     : { 8'h00, datas[7:0] }; 
\newline

assign dataout = bswap ? { N[7:0], N[l-1:8] }
\newline

                       : N; 
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\newline

@
\end_layout

\begin_layout Standard
Memory access can't just be done word wise, but also byte wise.
 Therefore two write lines exist.
 For byte wise store the lower byte of T is copied to the higher one.
\end_layout

\begin_layout Scrap
<<load/store>>=
\newline

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5'b10000, 5'b10001, 5'b10100, 5'b10101:
\newline

begin        // !+, @+, c!+, c@+
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\newline

   if(nextstate != 2'b10) T <= incaddr;
\newline

   sp <= rd ? spdec : spinc;
\newline

end
\newline

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5'b10010, 5'b10011, 5'b10110, 5'b10111:
\newline

   T <= dataw;  // @, lit, c@, litc
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\newline

@
\end_layout

\begin_layout Standard
Memory accesses need an extra cycle.
 Here the result of the memory access is handled.
\end_layout

\begin_layout Scrap
<<load-store>>=
\newline

<<pointer increment>>
\newline

if(|state[1:0]) begin 
\newline

   <<store afterwork>>
\newline

end else begin 
\newline

   <<ifetch>>
\newline

end
\newline

@
\end_layout

\begin_layout Scrap
<<debug>>=
\newline

$write("%b[%b] T=%b%x:%x[%x], ",
\newline

       inst, state, c, T, N, sp);
\newline

$write("P=%x, I=%x, R=%x[%x], res=%b%x
\backslash
n",
\newline

       P, I, R, rp, carry, res);
\newline

@
\end_layout

\begin_layout Standard
After the access is completed, the result for a load has to be pushed on
 the stack, or into the instruction register; for stores, the TOS is to
 be dropped.
\end_layout

\begin_layout Scrap
<<store afterwork>>=
\newline

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if(rd && { inst[4:3], inst[1:0] } != 4'b1010)
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\newline

   sp <= spdec;
\newline

if(|wr) sp <= spinc;
\newline

@
\end_layout

\begin_layout Standard
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Furthermore, the incremented address may go back to the program pointer.
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\end_layout

\begin_layout Scrap
<<pointer increment>>=
\newline

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if(~|state || 
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\newline

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   ({ inst[4:3], inst[1:0] } == 4'b1011))
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\newline

   P <= incaddr;
\newline

@
\end_layout

\begin_layout Standard
To shortcut a 
\family typewriter
nop
\family default
 in the first instruction, there's some special logic.
 That's the second part of NEXT.
\end_layout

\begin_layout Scrap
<<ifetch>>=
\newline

I <= data; 
\newline

if(!data[15]) state[1:0] <= 2'b01;
\newline

@
\end_layout

\begin_layout Subsubsection
Peripherals
\end_layout

\begin_layout Standard
Peripherals should only use address bits [15:1], read a whole word, and
 select the bytes written to based on the two write bits (bit 1 for most
 significant byte, bit 0 for least significant byte).
\end_layout

\begin_layout Subsection
Stack Instructions
\end_layout

\begin_layout Standard
Stack instructions change the stack pointer and move values into and out
 of latches.
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 With the 6 used stack operations, one notes that 
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\family typewriter
swap
\family default
 is missing.
 Instead, there's 
\family typewriter
nip
\family default
.
 The reason is a possible implementation option: it's possible to omit N,
 and fetch this value directly out of the stack RAM.
 This consumes more time, but saves space.
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
nip ( a b---b )
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
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drop ( a--- )
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\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
over ( a b---a b a )
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
dup ( a---a a )
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
>r ( a---r:a )
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Description
r> ( r:a---a )
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Scrap
<<stack operations>>=
\newline

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5'b11000: sp <= spinc;               // nip
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\newline

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5'b11001: `DROP;                     // drop
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\newline

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5'b11010: { sp, T } <= { spdec, N }; // over
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\newline

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5'b11011: sp <= spdec;               // dup
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\newline

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5'b11100: begin                      // >r
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\newline

   R <= T; rp <= rpdec; `DROP;
\newline

end // case: 5'b11100
\newline

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5'b11110: begin                      // r>
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\newline

   { sp, T, R } <= { spdec, R, toR };
\newline

   rp <= rpinc;
\newline

end // case: 5'b11110
\newline

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default ;                            // noop
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\newline

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@
\end_layout

\begin_layout Section
The Rest of the Implementation
\end_layout

\begin_layout Standard
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First the implementation file(s) with comment and modules.
 You can either have all in one file (
\family typewriter
b16.v
\family default
), or each module in a file with the same name as the module---the defines
 will go to 
\family typewriter
b16-defines.v
\family default
 for central manipulation of the defines.
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\end_layout

\begin_layout Scrap
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<<header>>=
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\newline

/*
\newline

 * b16 core: 16 bits, 
\newline

 * inspired by c18 core from Chuck Moore
\newline

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 * (c) 2002-2011 by Bernd Paysan
\newline

 * 
\newline

 * <<gpl-header>>
\newline

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 */
\newline

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@
\end_layout

\begin_layout Scrap
<<defines>>=
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\newline

`define L [l-1:0]
\newline

`define DROP { sp, T } <= { spinc, N } 
\newline

`define DEBUGGING
\newline

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`define FPGA
\newline

// `define BUSTRI
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\newline

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@
\end_layout

\begin_layout Scrap
<<b16.v>>=
\newline

<<header>>
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\newline

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/*
\newline

<<inst-comment>>
\newline

 */
\newline

<<defines>>
\newline

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\newline

<<ALU>>
\newline

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<<latchen>>
\newline

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<<Stack>>
\newline

<<cpu>>
\newline

<<debugger>>
\newline

@
\end_layout

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\begin_layout Scrap
<<b16-defines.v>>=
\newline

<<defines>>
\newline

@
\end_layout

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\begin_layout Scrap
<<alu.v>>=
\newline

<<header>>
\newline

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`include "b16-defines.v"
\newline

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\newline

<<ALU>>
\newline

@
\end_layout

\begin_layout Scrap
<<stack.v>>=
\newline

<<header>>
\newline

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`include "b16-defines.v"
\newline

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\newline

<<Stack>>
\newline

@
\end_layout

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\begin_layout Scrap
<<latchen.v>>=
\newline

<<header>>
\newline

`include "b16-defines.v"
\newline


\newline

<<latchen>>
\newline

@
\end_layout

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\begin_layout Scrap
<<cpu.v>>=
\newline

<<header>>
\newline

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/*
\newline

<<inst-comment>>
\newline

 */
\newline

`include "b16-defines.v"
\newline

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\newline

<<cpu>>
\newline

@
\end_layout

\begin_layout Scrap
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<<debugger.v>>=
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\newline

<<header>>
\newline

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`include "b16-defines.v"
\newline

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\newline

<<debugger>>
\newline

@
\end_layout

\begin_layout Scrap
<<gpl-header>>=
\newline

This program is free software; you can redistribute it and/or modify
\newline

it under the terms of the GNU General Public License as published by
\newline

the Free Software Foundation; version 2 of the License or any later.
\newline


\newline

This program is distributed in the hope that it will be useful,
\newline

but WITHOUT ANY WARRANTY; without even the implied warranty of
\newline

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  See the
\newline

GNU General Public License for more details.
\newline


\newline

This is not the source code of the program, the source code is a LyX
\newline

literate programming style article.
\newline

@
\end_layout

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\begin_layout Scrap
<<inst-comment>>= 
\newline

 * Instruction set:
\newline

 * 1, 5, 5, 5 bits
\newline

 *     0    1    2    3    4    5    6    7
\newline

 *  0: nop  call jmp  ret  jz   jnz  jc   jnc
\newline

 *  /3      exec goto ret  gz   gnz  gc   gnc
\newline

 *  8: xor  com  and  or   +    +c   *+   /-
\newline

 * 10: !+   @+   @    lit  c!+  c@+  c@   litc
\newline

 *  /1 !.
   @.
   @    lit  c!.
  c@.
  c@   litc
\newline

 * 18: nip  drop over dup  >r        r>
\newline

@
\end_layout

\begin_layout Subsection
Top Level
\end_layout

\begin_layout Standard
The CPU consists of several parts, which are all implemented in the same
 Verilog module.
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Scrap
<<cpu>>=
\newline

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module cpu(clk, run, nreset, addr, rd, wr, data, 
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\newline

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           dataout, scanning, atpg 
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\newline

`ifdef DEBUGGING,
\newline

           dr, dw, daddr, din, dout, bp`endif);
\newline

   <<port declarations>>
\newline

   <<register declarations>>
\newline

   <<instruction selection>>
\newline

   <<ALU instantiation>>
\newline

   <<address handling>>
\newline

   <<stack pushs>>
\newline

   <<stack instantiation>>
\newline

   <<state changes>>
\newline

   <<debugging read>>
\newline


\newline

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   always @(posedge clk or negedge nreset)
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\newline

      <<register updates>>
\newline


\newline

endmodule // cpu
\newline

@
\end_layout

\begin_layout Standard
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First, Verilog needs port declarations, so that it can know what's input
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 and output.
 The parameter are used to configure other word sizes and stack depths.
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 The CPU is not fully scalable, e.g.
 the instruction decoder or the byte swap operation for byte access depends
 on 16 bit word size, but those parts of the CPU that are scalable can be
 scaled by changing that parameter---the others need manual intervention.
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\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Scrap
<<port declarations>>=
\newline

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parameter rstaddr=16'h3FFE, show=0,
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\newline

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          l=16, sdep=4, rdep=4;
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\newline

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input clk, run, nreset, scanning, atpg;
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\newline

output `L addr;
\newline

output rd;
\newline

output [1:0] wr;
\newline

input  `L data;
\newline

output `L dataout;
\newline

<<debugging-ports>>
\newline

@
\end_layout

\begin_layout Standard
The ALU is instantiated with the configured width, and the necessary wires
 are declared
\end_layout

\begin_layout Scrap
<<ALU instantiation>>=
\newline

wire `L res, toN, toR, N;
\newline

wire carry, zero;
\newline


\newline

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alu #(l) alu16(.res(res), .carry(carry),
\newline

               .zero(zero), 
\newline

               .T(T), .N(N), .c(c),
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\newline

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               .inst(inst[2:0]));
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\newline

@
\end_layout

\begin_layout Standard
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Since the stacks work in parallel, we have to calculate when a value is
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 pushed onto the stack (thus 
\series bold
only
\series default
 if something is stored there).
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Scrap
<<stack pushs>>=
\newline

reg dpush, rpush;
\newline


\newline

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always @(state or inst or rd or run <<dbg senselist>>)
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\newline

  begin
\newline

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     rpush = 1'b0;
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\newline

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     dpush = (|state[1:0] & rd) |
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\newline

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             (inst[4] && inst[3] && inst[1]);
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\newline

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     case(inst)
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\newline

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        5'b00001: rpush = |state[1:0] | run;
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\newline

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        5'b11100: rpush = 1'b1;
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\newline

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        default ;
\newline

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     endcase // case(inst)
\newline

     <<stack debugging>>
\newline

  end
\newline

@
\end_layout

\begin_layout Standard
The stacks don't only consist of the two stack modules, but also need an
 incremented and decremented stack pointer.
 The return stack even allows to write the top of return stack even without
 changing the return stack depth.
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Scrap
<<stack instantiation>>=
\newline

wire [sdep-1:0] spdec, spinc;
\newline

wire [rdep-1:0] rpdec, rpinc;
\newline


\newline

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stack #(sdep,l) dstack(.clk(clk),
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\newline

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                       .sp(sp),
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\newline

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                       .spdec(spdec),
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\newline

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                       .push(dpush),
\newline

                       .in(toN),
\newline

                       .out(N),
\newline

                       .scan(scanning));
\newline

stack #(rdep,l) rstack(.clk(clk),
\newline

                       .sp(rp),
\newline

                       .spdec(rpdec),
\newline

                       .push(rpush),
\newline

                       .in(R),
\newline

                       .out(toR),
\newline

                       .scan(scanning));
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\newline


\newline

assign spdec = sp-{{(sdep-1){1'b0}}, 1'b1};
\newline

assign spinc = sp+{{(sdep-1){1'b0}}, 1'b1};
\newline

assign rpdec = rp-{{(rdep-1){1'b0}}, 1'b1};
\newline

assign rpinc = rp+{{(rdep-1){1'b0}}, 1'b1};
\newline

@
\end_layout

\begin_layout Standard
The basic core is the fully synchronous register update.
 Each register needs a reset value, and depending on the state transition,
 the corresponding assignments have to be coded.
 Most of that is from above, only the instruction fetch and the assignment
 of the next value of 
\family typewriter
incby
\family default
 has to be done.
\begin_inset ERT
status collapsed

\begin_layout Standard


\backslash
filbreak
\end_layout

\end_inset


\end_layout

\begin_layout Scrap
<<register updates>>=
\newline

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if(!nreset) begin
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\newline

   <<resets>>
\newline

end else if(run) begin