Commit cf3c099f authored by bp's avatar bp

Lattice port

git-svn-id: https://www.forth-ev.de/repos/b16-small@2033 3b8d8251-53f3-0310-8f3b-fd1cb8370982
parent 09873ac4
<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="1.3" title="b16" device="LFE2-12E-5F256C" synthesis="synplify" default_implementation="b16">
<BaliProject version="1.3" title="b16" device="LFEC10E-5F484C" synthesis="synplify" default_implementation="b16">
<Options/>
<Implementation title="b16" dir="b16" description="b16" default_strategy="I/O Assistant">
<Implementation title="b16" dir="b16" description="b16" default_strategy="Timing">
<Options/>
<Source name="b16.v" type="Verilog" type_short="Verilog">
<Options/>
......@@ -24,6 +24,15 @@
<Source name="uart.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="bootram_lattice.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="bootramh.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="bootraml.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="b16.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
......
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