Commit e24f389e authored by bp's avatar bp

Added global write to latches

git-svn-id: https://www.forth-ev.de/repos/b16-small@1880 3b8d8251-53f3-0310-8f3b-fd1cb8370982
parent 8b2e4cbe
......@@ -6,7 +6,7 @@ LYXREV = # set e.g. to 14 for LyX 1.4
all: b16.v b16-fig.eps b16-fig.pdf b16.pdf
files: cpu.v stack.v alu.v debugger.v latchen.v b16-defines.v
files: cpu.v stack.v alu.v debugger.v b16-defines.v
%.nw: %.lyx$(LYXREV)
-rm $@
......
......@@ -21,7 +21,7 @@ module b16_eval(clk, reset, din, dout, a, d, wr_b, rd_b, ble_b, bhe_b);
wire intreq = 0;
wire nreset = ~reset;
cpu b16(clk, 1'b1, nreset, addr, r, w, data, dwrite, 1'b1, 1'b0, 1'b0
cpu b16(clk, clk, 1'b1, nreset, addr, r, w, data, dwrite, 1'b0
`ifdef DEBUGGING, dr, dw, daddr, din, dout, bp`endif);
assign d = r ? {(l){ 1'bz }} : dwrite;
......
......@@ -2959,10 +2959,6 @@ b16-defines.v
\begin_inset Newline newline
\end_inset
<<latchen>>
\begin_inset Newline newline
\end_inset
<<Stack>>
\begin_inset Newline newline
\end_inset
......@@ -3038,30 +3034,6 @@ b16-defines.v
@
\end_layout
\begin_layout Scrap
<<latchen.v>>=
\begin_inset Newline newline
\end_inset
<<header>>
\begin_inset Newline newline
\end_inset
`include "b16-defines.v"
\begin_inset Newline newline
\end_inset
\begin_inset Newline newline
\end_inset
<<latchen>>
\begin_inset Newline newline
\end_inset
@
\end_layout
\begin_layout Scrap
<<cpu.v>>=
\begin_inset Newline newline
......@@ -3250,11 +3222,11 @@ filbreak
\begin_inset Newline newline
\end_inset
module cpu(clk, run, nreset, addr, rd, wr, data,
module cpu(clk, latclk, run, nreset, addr, rd, wr, data,
\begin_inset Newline newline
\end_inset
dataout, scanning, atpg
dataout, gwrite
\begin_inset Newline newline
\end_inset
......@@ -3361,7 +3333,7 @@ parameter rstaddr=16'h3FFE, show=0,
\begin_inset Newline newline
\end_inset
input clk, run, nreset, scanning, atpg;
input clk, latclk, run, nreset, gwrite;
\begin_inset Newline newline
\end_inset
......@@ -3556,7 +3528,7 @@ wire [rdep-1:0] rpdec, rpinc;
\begin_inset Newline newline
\end_inset
stack #(sdep,l) dstack(.clk(clk),
stack #(sdep,l) dstack(.clk(latclk),
\begin_inset Newline newline
\end_inset
......@@ -3580,11 +3552,11 @@ stack #(sdep,l) dstack(.clk(clk),
\begin_inset Newline newline
\end_inset
.scan(scanning));
.gwrite(gwrite));
\begin_inset Newline newline
\end_inset
stack #(rdep,l) rstack(.clk(clk),
stack #(rdep,l) rstack(.clk(latclk),
\begin_inset Newline newline
\end_inset
......@@ -3608,7 +3580,7 @@ stack #(rdep,l) rstack(.clk(clk),
\begin_inset Newline newline
\end_inset
.scan(scanning));
.gwrite(gwrite));
\begin_inset Newline newline
\end_inset
......@@ -4836,7 +4808,7 @@ filbreak
\begin_inset Newline newline
\end_inset
module stack(clk, sp, spdec, push, scan, in, out);
module stack(clk, sp, spdec, push, gwrite, in, out);
\begin_inset Newline newline
\end_inset
......@@ -4844,7 +4816,7 @@ module stack(clk, sp, spdec, push, scan, in, out);
\begin_inset Newline newline
\end_inset
input clk, push, scan;
input clk, push, gwrite;
\begin_inset Newline newline
\end_inset
......@@ -4876,35 +4848,35 @@ module stack(clk, sp, spdec, push, scan, in, out);
\begin_inset Newline newline
\end_inset
wire write;
reg [dep-1:0] i;
\begin_inset Newline newline
\end_inset
latchen genwrite(.clk(clk),
\begin_inset Newline newline
\end_inset
.en(push),
always @(clk or push or gwrite or spdec or in)
\begin_inset Newline newline
\end_inset
.scan(scan),
if(~clk)
\begin_inset Newline newline
\end_inset
.out(write));
if(gwrite)
\begin_inset Newline newline
\end_inset
for(i=0; i<(1@<<dep); i=i+1)
\begin_inset Newline newline
\end_inset
always @(write or spdec or in)
stackmem[i] <= in;
\begin_inset Newline newline
\end_inset
if(write) stackmem[spdec] <= in;
else if(push) stackmem[spdec] <= in;
\begin_inset Newline newline
\end_inset
......@@ -4944,46 +4916,6 @@ endmodule // stack
\begin_inset Newline newline
\end_inset
@
\end_layout
\begin_layout Scrap
<<latchen>>=
\begin_inset Newline newline
\end_inset
`ifndef FPGA
\begin_inset Newline newline
\end_inset
module latchen(clk, en, scan, out);
\begin_inset Newline newline
\end_inset
input clk, en, scan;
\begin_inset Newline newline
\end_inset
output out;
\begin_inset Newline newline
\end_inset
\begin_inset Newline newline
\end_inset
assign out = en & ~clk & ~scan;
\begin_inset Newline newline
\end_inset
endmodule
\begin_inset Newline newline
\end_inset
`endif
\begin_inset Newline newline
\end_inset
@
\begin_inset Newline newline
\end_inset
......
No preview for this file type
......@@ -59,17 +59,9 @@ module alu(res, carry, zero, T, N, c, inst);
assign carry = carries[l];
assign zero = ~|T;
endmodule // alu
`ifndef FPGA
module latchen(clk, en, scan, out);
input clk, en, scan;
output out;
assign out = en & ~clk & ~scan;
endmodule
`endif
module stack(clk, sp, spdec, push, scan, in, out);
module stack(clk, sp, spdec, push, gwrite, in, out);
parameter dep=2, l=16;
input clk, push, scan;
input clk, push, gwrite;
input [dep-1:0] sp, spdec;
input `L in;
output `L out;
......@@ -77,14 +69,14 @@ module stack(clk, sp, spdec, push, scan, in, out);
reg `L stackmem[0:(1<<dep)-1];
`ifndef FPGA
wire write;
latchen genwrite(.clk(clk),
.en(push),
.scan(scan),
.out(write));
reg [dep-1:0] i;
always @(write or spdec or in)
if(write) stackmem[spdec] <= in;
always @(clk or push or gwrite or spdec or in)
if(~clk)
if(gwrite)
for(i=0; i<(1<<dep); i=i+1)
stackmem[i] <= in;
else if(push) stackmem[spdec] <= in;
`else
always @(posedge clk)
if(push)
......@@ -94,13 +86,13 @@ module stack(clk, sp, spdec, push, scan, in, out);
assign out = stackmem[sp];
endmodule // stack
module cpu(clk, run, nreset, addr, rd, wr, data,
dataout, scanning, atpg
module cpu(clk, latclk, run, nreset, addr, rd, wr, data,
dataout, gwrite
`ifdef DEBUGGING,
dr, dw, daddr, din, dout, bp`endif);
parameter rstaddr=16'h3FFE, show=0,
l=16, sdep=4, rdep=4;
input clk, run, nreset, scanning, atpg;
input clk, latclk, run, nreset, gwrite;
output `L addr;
output rd;
output [1:0] wr;
......@@ -191,20 +183,20 @@ module cpu(clk, run, nreset, addr, rd, wr, data,
wire [sdep-1:0] spdec, spinc;
wire [rdep-1:0] rpdec, rpinc;
stack #(sdep,l) dstack(.clk(clk),
stack #(sdep,l) dstack(.clk(latclk),
.sp(sp),
.spdec(spdec),
.push(dpush),
.in(toN),
.out(N),
.scan(scanning));
stack #(rdep,l) rstack(.clk(clk),
.gwrite(gwrite));
stack #(rdep,l) rstack(.clk(latclk),
.sp(rp),
.spdec(rpdec),
.push(rpush),
.in(R),
.out(toR),
.scan(scanning));
.gwrite(gwrite));
assign spdec = sp-{{(sdep-1){1'b0}}, 1'b1};
assign spinc = sp+{{(sdep-1){1'b0}}, 1'b1};
......
......@@ -216,7 +216,7 @@ assign I2C_SDAT = 1'bz;
addr, r,
drun, dr, dw, bp);
cpu b16(clk, run, nreset, addrc, rc, wc, data, dwritec, 1'b0, 1'b0,
cpu b16(clk, clk, run, nreset, addrc, rc, wc, data, dwritec, 1'b0,
dr, dw, addru[3:1], datau, data_dbg, bp);
SEG7_LUT_4 u0 ( HEX0,HEX1,HEX2,HEX3, /*SW[2] ? SW[0] ? { 8'h0, dix, ru, wru, 1'b0, dstate } : rate : SW[1] ? (SW[0] ? addr : data) :*/ LED7);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment