Commit ffd806c0 authored by uho's avatar uho

Sort-of works on Altera (w/o SRAM)

git-svn-id: https://www.forth-ev.de/repos/b16-small@1114 3b8d8251-53f3-0310-8f3b-fd1cb8370982
parent 88957b81
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module SEG7_LUT ( oSEG,iDIG );
input [3:0] iDIG;
output [6:0] oSEG;
reg [6:0] oSEG;
always @(iDIG)
begin
case(iDIG)
4'h1: oSEG = 7'b1111001; // ---t----
4'h2: oSEG = 7'b0100100; // | |
4'h3: oSEG = 7'b0110000; // lt rt
4'h4: oSEG = 7'b0011001; // | |
4'h5: oSEG = 7'b0010010; // ---m----
4'h6: oSEG = 7'b0000010; // | |
4'h7: oSEG = 7'b1111000; // lb rb
4'h8: oSEG = 7'b0000000; // | |
4'h9: oSEG = 7'b0011000; // ---b----
4'ha: oSEG = 7'b0001000;
4'hb: oSEG = 7'b0000011;
4'hc: oSEG = 7'b1000110;
4'hd: oSEG = 7'b0100001;
4'he: oSEG = 7'b0000110;
4'hf: oSEG = 7'b0001110;
4'h0: oSEG = 7'b1000000;
endcase
end
endmodule
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module SEG7_LUT_4 ( oSEG0,oSEG1,oSEG2,oSEG3,iDIG );
input [15:0] iDIG;
output [6:0] oSEG0,oSEG1,oSEG2,oSEG3;
SEG7_LUT u0 ( oSEG0,iDIG[3:0] );
SEG7_LUT u1 ( oSEG1,iDIG[7:4] );
SEG7_LUT u2 ( oSEG2,iDIG[11:8] );
SEG7_LUT u3 ( oSEG3,iDIG[15:12] );
endmodule
\ No newline at end of file
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 132 02/25/2009 SJ Web Edition
# Date created = 11:58:38 March 26, 2009
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "11:58:38 March 26, 2009"
# Revisions
PROJECT_REVISION = "b16top"
......@@ -16,7 +16,7 @@
`define L [l-1:0]
`define DROP { sp, T } <= { spinc, N }
`define DEBUGGING
// `define FPGA
`define FPGA
`timescale 1ns / 1ns
module alu(res, carry, zero, T, N, c, inst);
......@@ -101,7 +101,7 @@ module cpu(clk, run, reset, addr, rd, wr, data,
dataout, READY, scanning, atpg
`ifdef DEBUGGING,
dr, dw, daddr, din, dout, bp`endif);
parameter rstaddr=16'h07FE, show=0,
parameter rstaddr=16'h3FFE, show=0,
l=16, sdep=2, rdep=2;
input clk, run, reset, READY, scanning, atpg;
output `L addr;
......@@ -207,6 +207,9 @@ module cpu(clk, run, reset, addr, rd, wr, data,
state[1:0] + 2'b01 : 2'b00;
`ifdef DEBUGGING
reg `L dout;
// SEG7_LUT_4 u0 ( HEX0,HEX1,HEX2,HEX3, P );
always @(daddr or dr or run or P or T or R or I or
state or sp or rp or c or N or toR or bp)
......
This diff is collapsed.
module b16top
(
//////////////////// Clock Input ////////////////////
CLOCK_24, // 24 MHz
CLOCK_27, // 27 MHz
CLOCK_50, // 50 MHz
EXT_CLOCK, // External Clock
//////////////////// Push Button ////////////////////
KEY, // Pushbutton[3:0]
//////////////////// DPDT Switch ////////////////////
SW, // Toggle Switch[9:0]
//////////////////// 7-SEG Dispaly ////////////////////
HEX0, // Seven Segment Digit 0
HEX1, // Seven Segment Digit 1
HEX2, // Seven Segment Digit 2
HEX3, // Seven Segment Digit 3
//////////////////////// LED ////////////////////////
LEDG, // LED Green[7:0]
LEDR, // LED Red[9:0]
//////////////////////// UART ////////////////////////
UART_TXD, // UART Transmitter
UART_RXD, // UART Receiver
///////////////////// SDRAM Interface ////////////////
DRAM_DQ, // SDRAM Data bus 16 Bits
DRAM_ADDR, // SDRAM Address bus 12 Bits
DRAM_LDQM, // SDRAM Low-byte Data Mask
DRAM_UDQM, // SDRAM High-byte Data Mask
DRAM_WE_N, // SDRAM Write Enable
DRAM_CAS_N, // SDRAM Column Address Strobe
DRAM_RAS_N, // SDRAM Row Address Strobe
DRAM_CS_N, // SDRAM Chip Select
DRAM_BA_0, // SDRAM Bank Address 0
DRAM_BA_1, // SDRAM Bank Address 0
DRAM_CLK, // SDRAM Clock
DRAM_CKE, // SDRAM Clock Enable
//////////////////// Flash Interface ////////////////
FL_DQ, // FLASH Data bus 8 Bits
FL_ADDR, // FLASH Address bus 22 Bits
FL_WE_N, // FLASH Write Enable
FL_RST_N, // FLASH Reset
FL_OE_N, // FLASH Output Enable
FL_CE_N, // FLASH Chip Enable
//////////////////// SRAM Interface ////////////////
SRAM_DQ, // SRAM Data bus 16 Bits
SRAM_ADDR, // SRAM Address bus 18 Bits
SRAM_UB_N, // SRAM High-byte Data Mask
SRAM_LB_N, // SRAM Low-byte Data Mask
SRAM_WE_N, // SRAM Write Enable
SRAM_CE_N, // SRAM Chip Enable
SRAM_OE_N, // SRAM Output Enable
//////////////////// SD_Card Interface ////////////////
SD_DAT, // SD Card Data
SD_DAT3, // SD Card Data 3
SD_CMD, // SD Card Command Signal
SD_CLK, // SD Card Clock
//////////////////// USB JTAG link ////////////////////
TDI, // CPLD -> FPGA (data in)
TCK, // CPLD -> FPGA (clk)
TCS, // CPLD -> FPGA (CS)
TDO, // FPGA -> CPLD (data out)
//////////////////// I2C ////////////////////////////
I2C_SDAT, // I2C Data
I2C_SCLK, // I2C Clock
//////////////////// PS2 ////////////////////////////
PS2_DAT, // PS2 Data
PS2_CLK, // PS2 Clock
//////////////////// VGA ////////////////////////////
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_R, // VGA Red[3:0]
VGA_G, // VGA Green[3:0]
VGA_B, // VGA Blue[3:0]
//////////////// Audio CODEC ////////////////////////
AUD_ADCLRCK, // Audio CODEC ADC LR Clock
AUD_ADCDAT, // Audio CODEC ADC Data
AUD_DACLRCK, // Audio CODEC DAC LR Clock
AUD_DACDAT, // Audio CODEC DAC Data
AUD_BCLK, // Audio CODEC Bit-Stream Clock
AUD_XCK, // Audio CODEC Chip Clock
//////////////////// GPIO ////////////////////////////
GPIO_0, // GPIO Connection 0
GPIO_1 // GPIO Connection 1
);
//////////////////////// Clock Input ////////////////////////
input [1:0] CLOCK_24; // 24 MHz
input [1:0] CLOCK_27; // 27 MHz
input CLOCK_50; // 50 MHz
input EXT_CLOCK; // External Clock
//////////////////////// Push Button ////////////////////////
input [3:0] KEY; // Pushbutton[3:0]
//////////////////////// DPDT Switch ////////////////////////
input [9:0] SW; // Toggle Switch[9:0]
//////////////////////// 7-SEG Dispaly ////////////////////////
output [6:0] HEX0; // Seven Segment Digit 0
output [6:0] HEX1; // Seven Segment Digit 1
output [6:0] HEX2; // Seven Segment Digit 2
output [6:0] HEX3; // Seven Segment Digit 3
//////////////////////////// LED ////////////////////////////
output [7:0] LEDG; // LED Green[7:0]
output [9:0] LEDR; // LED Red[9:0]
//////////////////////////// UART ////////////////////////////
output UART_TXD; // UART Transmitter
input UART_RXD; // UART Receiver
/////////////////////// SDRAM Interface ////////////////////////
inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
output DRAM_LDQM; // SDRAM Low-byte Data Mask
output DRAM_UDQM; // SDRAM High-byte Data Mask
output DRAM_WE_N; // SDRAM Write Enable
output DRAM_CAS_N; // SDRAM Column Address Strobe
output DRAM_RAS_N; // SDRAM Row Address Strobe
output DRAM_CS_N; // SDRAM Chip Select
output DRAM_BA_0; // SDRAM Bank Address 0
output DRAM_BA_1; // SDRAM Bank Address 0
output DRAM_CLK; // SDRAM Clock
output DRAM_CKE; // SDRAM Clock Enable
//////////////////////// Flash Interface ////////////////////////
inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
output FL_WE_N; // FLASH Write Enable
output FL_RST_N; // FLASH Reset
output FL_OE_N; // FLASH Output Enable
output FL_CE_N; // FLASH Chip Enable
//////////////////////// SRAM Interface ////////////////////////
inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
output SRAM_UB_N; // SRAM High-byte Data Mask
output SRAM_LB_N; // SRAM Low-byte Data Mask
output SRAM_WE_N; // SRAM Write Enable
output SRAM_CE_N; // SRAM Chip Enable
output SRAM_OE_N; // SRAM Output Enable
//////////////////// SD Card Interface ////////////////////////
inout SD_DAT; // SD Card Data
inout SD_DAT3; // SD Card Data 3
inout SD_CMD; // SD Card Command Signal
output SD_CLK; // SD Card Clock
//////////////////////// I2C ////////////////////////////////
inout I2C_SDAT; // I2C Data
output I2C_SCLK; // I2C Clock
//////////////////////// PS2 ////////////////////////////////
input PS2_DAT; // PS2 Data
input PS2_CLK; // PS2 Clock
//////////////////// USB JTAG link ////////////////////////////
input TDI; // CPLD -> FPGA (data in)
input TCK; // CPLD -> FPGA (clk)
input TCS; // CPLD -> FPGA (CS)
output TDO; // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output [3:0] VGA_R; // VGA Red[3:0]
output [3:0] VGA_G; // VGA Green[3:0]
output [3:0] VGA_B; // VGA Blue[3:0]
//////////////////// Audio CODEC ////////////////////////////
output AUD_ADCLRCK; // Audio CODEC ADC LR Clock
input AUD_ADCDAT; // Audio CODEC ADC Data
output AUD_DACLRCK; // Audio CODEC DAC LR Clock
output AUD_DACDAT; // Audio CODEC DAC Data
inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
output AUD_XCK; // Audio CODEC Chip Clock
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0; // GPIO Connection 0
inout [35:0] GPIO_1; // GPIO Connection 1
////////////////////////////////////////////////////////////////////
// All inout port turn to tri-state
assign DRAM_DQ = 16'hzzzz;
assign FL_DQ = 8'hzz;
assign SRAM_DQ = 16'hzzzz;
assign SD_DAT = 1'bz;
assign I2C_SDAT = 1'bz;
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
// SEG7_LUT_4 u0 ( HEX0,HEX1,HEX2,HEX3,{~SW[7:0],Cont[27:20]} );
reg [27:0] counter;
always@(posedge CLOCK_50) counter <= counter+1'b1;
wire clk = CLOCK_50;
wire nreset = KEY[0];
wire r;
wire [1:0] w;
wire [15:0] dwrite, addr;
reg [15:0] data, addr_i;
reg [2:0] sel;
cpu b16(clk, &counter[22:0], nreset, addr, r, w, data, dwrite, 1'b1, 1'b0, 1'b0
`ifdef DEBUGGING, dr, dw, daddr, din, dout, bp`endif);
SEG7_LUT_4 u0 ( HEX0,HEX1,HEX2,HEX3, addr );
reg [7:0] bootraml[0:4095], bootramh[0:4095];
always @(negedge clk)
begin
addr_i <= addr;
if(sel[1]) begin
if(w[1]) bootramh[addr[12:1]] <= dwrite[15:8];
if(w[0]) bootraml[addr[12:1]] <= dwrite[ 7:0];
end
end
always @(r or sel or addr_i or SRAM_DQ)
casez({ r, sel })
// 4'b1100: data <= addr[1] ? dout_out : din;
4'b1010: data <= { bootramh[addr_i[12:1]], bootraml[addr_i[12:1]] };
4'b1001: data <= SRAM_DQ;
4'b????: data <= 16'h0000;
endcase // case(sel)
always @(addr)
if(addr[15:2] == 14'h3fff) sel <= 3'b100;
else if(addr[15:13] == 3'h1) sel <= 3'b010;
else sel <= 3'b001;
assign SRAM_WE_N = ~(sel[0] & |w);
assign SRAM_CE_N = ~sel[0] | (|w & clk);
assign SRAM_OE_N = ~(sel[0] & r);
assign SRAM_DQ = SRAM_OE_N ? dwrite : 16'hzzzz;
assign SRAM_ADDR = ~sel[0] ? 16'hzzzz : addr[15:1];
assign SRAM_UB_N = SRAM_WE_N | ~w[1];
assign SRAM_LB_N = SRAM_WE_N | ~w[0];
initial
begin
$readmemh("b16l.hex", bootraml);
$readmemh("b16h.hex", bootramh);
end
endmodule
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