Skip to content

B
b16-small
Commit eefd5fc4 authored by bp's avatar bp
Browse files
Options

Lattice port 

git-svn-id: https://www.forth-ev.de/repos/b16-small@2030 3b8d8251-53f3-0310-8f3b-fd1cb8370982
parent 1838641e
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 2165 additions and 2090 deletions
b16.fs
View file @ eefd5fc4
......@@ -377,6 +377,29 @@ $800 Value rom-end
I over - 1+ 0 <# I ram@ 0 # # 2drop bl hold # # # # '@ hold #>
fd write-line throw
2 +LOOP fd close-file throw drop decimal ;
: .hex' ( start n "file" -- ) over swap hex
parse-name new-fd
bounds ?DO
I over - 2/ 0 <# I ram@ 0 # # # # 2drop #>
fd write-line throw 2 +LOOP fd close-file throw drop decimal ;
: .hexl' ( start n "file" -- ) over swap hex
parse-name new-fd
bounds ?DO
I over - 2/ 0 <# I ram@ 0 # # 2drop #>
fd write-line throw 2 +LOOP fd close-file throw drop decimal ;
: .hexh' ( start n "file" -- ) over swap hex
parse-name new-fd
bounds ?DO
I over - 2/ 0 <# I ram@ 8 rshift 0 # # 2drop #>
fd write-line throw 2 +LOOP fd close-file throw drop decimal ;
: .hexb' ( start n "file" -- ) over swap hex
parse-name new-fd
bounds ?DO
I over - 0 <# I ram@ 8 rshift 0 # # 2drop #>
fd write-line throw
I over - 1+ 0 <# I ram@ 0 # # 2drop #>
fd write-line throw
2 +LOOP fd close-file throw drop decimal ;
: .end inst, ;
: ;; inst, ;
: macro: : ;
......
b16.ldf 0 → 100644
View file @ eefd5fc4
<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="1.3" title="b16" device="LFE2-12E-5F256C" synthesis="synplify" default_implementation="b16">
<Options/>
<Implementation title="b16" dir="b16" description="b16" default_strategy="I/O Assistant">
<Options/>
<Source name="b16.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="b16top.v" type="Verilog" type_short="Verilog">
<Options top_module="b16top"/>
</Source>
<Source name="dbg_uart.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="SEG7_LUT_4.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="SEG7_LUT.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="sfr.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="uart.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="b16.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="Strategy1.sty"/>
</BaliProject>
b16.lyx
View file @ eefd5fc4
......@@ -2380,7 +2380,7 @@ wire `L incaddr, dataw, datas;
\end_layout
\begin_layout Scrap
wire tos2r, tos2n;
wire tos2n;
\end_layout
\begin_layout Scrap
......
b16.pdf
View file @ eefd5fc4
No preview for this file type
b16.v
View file @ eefd5fc4
......@@ -136,7 +136,7 @@ module cpu(clk, latclk, run, nreset, addr, rd, wr, data,
.T(T), .N(N), .c(c),
.inst(inst[2:0]));
wire `L incaddr, dataw, datas;
wire tos2r, tos2n;
wire tos2n;
wire incby, bswap, addrsel, access, rd;
wire [1:0] wr;
......
b16h.hex
View file @ eefd5fc4
This diff is collapsed.
b16l.hex
View file @ eefd5fc4
This diff is collapsed.
b16top.qsf
View file @ eefd5fc4
......@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name TOP_LEVEL_ENTITY b16top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:58:38 MARCH 26, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1"
set_global_assignment -name LAST_QUARTUS_VERSION 11.0
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
......@@ -503,12 +503,14 @@ set_global_assignment -name MISC_FILE "C:/cygwin/home/bernd/b16-small/b16top.dpf
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name VERILOG_FILE sfr.v
set_global_assignment -name VERILOG_FILE dbg_uart.v
set_global_assignment -name VERILOG_FILE uart.v
set_global_assignment -name VERILOG_FILE SEG7_LUT.v
set_global_assignment -name VERILOG_FILE SEG7_LUT_4.v
set_global_assignment -name VERILOG_FILE b16.v
set_global_assignment -name VERILOG_FILE b16top.v
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name VERILOG_FILE bootram.v
set_global_assignment -name VERILOG_FILE sfr.v
set_global_assignment -name VERILOG_FILE dbg_uart.v
set_global_assignment -name VERILOG_FILE uart.v
set_global_assignment -name VERILOG_FILE SEG7_LUT.v
set_global_assignment -name VERILOG_FILE SEG7_LUT_4.v
set_global_assignment -name VERILOG_FILE b16.v
set_global_assignment -name VERILOG_FILE b16top.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
b16top.v
View file @ eefd5fc4
......@@ -169,22 +169,32 @@ assign DRAM_DQ = 16'hzzzz;
assign FL_DQ = 8'hzz;
assign SRAM_DQ = 16'hzzzz;
assign SD_DAT = 1'bz;
assign I2C_SDAT = 1'bz;
assign I2C_SDAT = 1'bz;
// all unconnected outputs to harmless values
assign { DRAM_ADDR, DRAM_LDQM, DRAM_UDQM, DRAM_WE_N, DRAM_CAS_N, DRAM_RAS_N, DRAM_CS_N } = 'hF;
assign { DRAM_BA_0, DRAM_BA_1, DRAM_CLK, DRAM_CKE } = 0;
assign { FL_ADDR, FL_WE_N, FL_RST_N, FL_OE_N, FL_CE_N } = 'hF;
assign { SD_DAT3, SD_CMD, SD_CLK } = 0;
assign { VGA_HS, VGA_VS, VGA_R, VGA_G, VGA_B } = 0;
assign { AUD_ADCLRCK, AUD_DACLRCK, AUD_DACDAT, AUD_BCLK, AUD_XCK } = 0;
assign { TDO, I2C_SCLK } = 1;
reg [27:0] counter;
wire clk = CLOCK_50;
`ifdef SLOW_CLOCK
reg [27:0] counter;
always@(posedge clk or negedge nreset)
if(!nreset)
counter <= 0;
else
counter <= counter + 1;
`endif
wire nreset = KEY[0];
wire rc;
wire [1:0] wc;
wire [15:0] addrc, dwritec;
reg [15:0] data, addr_i;
reg [15:0] data;
reg [2:0] sel;
reg READY;
......@@ -194,17 +204,17 @@ assign I2C_SDAT = 1'bz;
wire dox;
wire dix, wip;
wire dr, drun, irqrun;
wire [1:0] dw, wru;
wire dr, dw, drun, irqrun;
wire [1:0] wru;
wire [2:0] dstate;
wire [15:0] caddr, cin, cout, LED7;
wire [15:0] addru, datau, data_dbg, bp;
wire [15:0] LED7;
wire [15:0] addru, datau, data_dbg, ramdata, bp;
wire run = irqrun & ~csu & drun & (/* SW[3] ? &counter[22:0] : */ &READY);
uart rs232(clk, nreset, UART_RXD, UART_TXD, id, od, dix, dox, wip, rate, LEDR);
dbg_uart dbgmem(clk, nreset, dix, dox, id, od,
csu, addru, ru, wru, dr ? data_dbg : data, datau, { 5'b00100, irqrun, &READY, drun });
csu, addru, ru, wru, dr ? data_dbg : data, datau, { 5'b00100, irqrun, &READY, drun }, dstate);
wire [15:0] addr = csu ? addru : addrc;
wire [15:0] dwrite = csu ? datau : dwritec;
......@@ -212,7 +222,7 @@ assign I2C_SDAT = 1'bz;
wire r = csu ? ru : rc;
debugger dbg(clk, nreset, ~csu & &READY,
addru, datau, ru, wru,
addru[15:1], datau, ru, wru,
addr, r,
drun, dr, dw, bp);
......@@ -221,21 +231,15 @@ assign I2C_SDAT = 1'bz;
SEG7_LUT_4 u0 ( HEX0,HEX1,HEX2,HEX3, /*SW[2] ? SW[0] ? { 8'h0, dix, ru, wru, 1'b0, dstate } : rate : SW[1] ? (SW[0] ? addr : data) :*/ LED7);
reg [7:0] bootraml[0:4095] /* synthesis ramstyle="no_rw_check" */;
reg [7:0] bootramh[0:4095] /* synthesis ramstyle="no_rw_check" */;
bootram bootmem(.clk(~clk), .nreset(nreset), .sel(sel[1]), .r(r), .w(w),
.addr(addr[12:1]), .din(dwrite), .dout(ramdata));
always @(negedge clk or negedge nreset)
if(!nreset) begin
READY <= -1;
addr_i <= 0;
end else begin
addr_i <= addr;
if(sel[0]) READY <= READY + 1;
else READY <= -1;
if(sel[1] & !r) begin
if(w[1]) bootramh[addr[12:1]] <= dwrite[15:8];
if(w[0]) bootraml[addr[12:1]] <= dwrite[ 7:0];
end
end
wire [15:0] sfr_data;
......@@ -243,18 +247,16 @@ assign I2C_SDAT = 1'bz;
sfr sfr_block(clk, nreset, drun, sel[2], addr[7:0], r, w, dwrite, sfr_data,
LED7, GPIO_0, GPIO_1, irqrun, { KEY[3:1], SW });
always @(r or w or sel or addr_i or SRAM_DQ)
begin
data <= 0;
casez({ r, sel })
4'b1100: data <= sfr_data;
4'b1010: data <= { bootramh[addr_i[12:1]], bootraml[addr_i[12:1]] };
4'b1001: data <= SRAM_DQ;
endcase // case(sel)
end
always @*
case({ r, sel })
4'b1100: data <= sfr_data;
4'b1010: data <= ramdata;
4'b1001: data <= SRAM_DQ;
default: data <= 0;
endcase // case(sel)
always @(addr)
if(addr[15:8] == 8'hff) sel <= 3'b100;
if(addr[15:8] == 8'hff) sel <= 3'b100;
else if(addr[15:13] == 3'h1) sel <= 3'b010;
else sel <= 3'b001;
......@@ -268,10 +270,4 @@ assign I2C_SDAT = 1'bz;
assign LEDG = { SRAM_WE_N, SRAM_CE_N, SRAM_OE_N, SRAM_UB_N, SRAM_LB_N, sel };
initial
begin
$readmemh("b16l.hex", bootraml);
$readmemh("b16h.hex", bootramh);
end
endmodule
bootramh.ipx 0 → 100644
View file @ eefd5fc4
<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="bootramh" module="RAM_DQ" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 07 26 01:10:44.414" version="7.1" type="Module" synthesis="synplify" source_format="Verilog">
<Package>
<File name="/home/bernd/proj/b16-small/b16h.mem" type="mem" modified="2011 07 25 22:03:51.000"/>
<File name="bootramh.lpc" type="lpc" modified="2011 07 26 01:10:41.000"/>
<File name="bootramh.v" type="top_level_verilog" modified="2011 07 26 01:10:41.000"/>
<File name="bootramh_tmpl.v" type="template_verilog" modified="2011 07 26 01:10:41.000"/>
<File name="tb_bootramh_tmpl.v" type="testbench_verilog" modified="2011 07 26 01:10:41.000"/>
</Package>
</DiamondModule>
bootraml.ipx 0 → 100644
View file @ eefd5fc4
<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="bootraml" module="RAM_DQ" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2011 07 26 01:11:20.246" version="7.1" type="Module" synthesis="synplify" source_format="Verilog">
<Package>
<File name="/home/bernd/proj/b16-small/b16l.mem" type="mem" modified="2011 07 25 22:03:51.000"/>
<File name="bootraml.lpc" type="lpc" modified="2011 07 26 01:11:16.000"/>
<File name="bootraml.v" type="top_level_verilog" modified="2011 07 26 01:11:16.000"/>
<File name="bootraml_tmpl.v" type="template_verilog" modified="2011 07 26 01:11:16.000"/>
<File name="tb_bootraml_tmpl.v" type="testbench_verilog" modified="2011 07 26 01:11:16.000"/>
</Package>
</DiamondModule>
cpu.v
View file @ eefd5fc4
......@@ -77,7 +77,7 @@ module cpu(clk, latclk, run, nreset, addr, rd, wr, data,
.T(T), .N(N), .c(c),
.inst(inst[2:0]));
wire `L incaddr, dataw, datas;
wire tos2r, tos2n;
wire tos2n;
wire incby, bswap, addrsel, access, rd;
wire [1:0] wr;
......
triceps.asm
View file @ eefd5fc4
......@@ -407,6 +407,8 @@ $3FFE org
$2000 $2000 .hex b16.hex \ print verilog hex for $2000 bytes
$2000 $2000 .hexh b16h.hex \ print verilog hex for $2000 bytes
$2000 $2000 .hexl b16l.hex \ print verilog hex for $2000 bytes
$2000 $2000 .hexh' b16h.mem \ print verilog hex for $2000 bytes, unaddressed
$2000 $2000 .hexl' b16l.mem \ print verilog hex for $2000 bytes, unaddressed
$2000 $2000 .hexb b16b.hex \ print verilog hex for $2000 bytes
.mif test.mif
\ $21FE org
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment