Commit eefd5fc4 authored by bp's avatar bp
Browse files

Lattice port 

git-svn-id: https://www.forth-ev.de/repos/b16-small@2030 3b8d8251-53f3-0310-8f3b-fd1cb8370982
parent 1838641e

b16.fs

+23 −0
Original line number Diff line number Diff line
@@ -377,6 +377,29 @@ $800 Value rom-end 
	I over - 1+ 0 <# I ram@          0 # # 2drop bl hold # # # # '@ hold #>

	fd write-line throw

    2 +LOOP fd close-file throw  drop decimal ;

: .hex' ( start n "file" -- ) over swap hex

    parse-name new-fd

    bounds ?DO

	I over - 2/ 0 <# I ram@ 0 # # # # 2drop #>

	fd write-line throw 2 +LOOP fd close-file throw  drop decimal ;

: .hexl' ( start n "file" -- ) over swap hex

    parse-name new-fd

    bounds ?DO

	I over - 2/ 0 <# I ram@ 0 # # 2drop #>

	fd write-line throw 2 +LOOP fd close-file throw  drop decimal ;

: .hexh' ( start n "file" -- ) over swap hex

    parse-name new-fd

    bounds ?DO

	I over - 2/ 0 <# I ram@ 8 rshift 0 # # 2drop #>

	fd write-line throw 2 +LOOP fd close-file throw  drop decimal ;

: .hexb' ( start n "file" -- ) over swap hex

    parse-name new-fd

    bounds ?DO

	I over -    0 <# I ram@ 8 rshift 0 # # 2drop #>

	fd write-line throw

	I over - 1+ 0 <# I ram@          0 # # 2drop #>

	fd write-line throw

    2 +LOOP fd close-file throw  drop decimal ;

: .end inst, ;

: ;; inst, ;

: macro: : ;

b16.ldf

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+32 −0
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<?xml version="1.0" encoding="UTF-8"?>

<BaliProject version="1.3" title="b16" device="LFE2-12E-5F256C" synthesis="synplify" default_implementation="b16">

    <Options/>

    <Implementation title="b16" dir="b16" description="b16" default_strategy="I/O Assistant">

        <Options/>

        <Source name="b16.v" type="Verilog" type_short="Verilog">

            <Options/>

        </Source>

        <Source name="b16top.v" type="Verilog" type_short="Verilog">

            <Options top_module="b16top"/>

        </Source>

        <Source name="dbg_uart.v" type="Verilog" type_short="Verilog">

            <Options/>

        </Source>

        <Source name="SEG7_LUT_4.v" type="Verilog" type_short="Verilog">

            <Options/>

        </Source>

        <Source name="SEG7_LUT.v" type="Verilog" type_short="Verilog">

            <Options/>

        </Source>

        <Source name="sfr.v" type="Verilog" type_short="Verilog">

            <Options/>

        </Source>

        <Source name="uart.v" type="Verilog" type_short="Verilog">

            <Options/>

        </Source>

        <Source name="b16.lpf" type="Logic Preference" type_short="LPF">

            <Options/>

        </Source>

    </Implementation>

    <Strategy name="Strategy1" file="Strategy1.sty"/>

</BaliProject>

b16.lyx

+1 −1
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@@ -2380,7 +2380,7 @@ wire `L incaddr, dataw, datas; 
\end_layout



\begin_layout Scrap

wire tos2r, tos2n;

wire tos2n;

\end_layout



\begin_layout Scrap

b16.pdf

+21 B (215 KiB)

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b16.v

+1 −1
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@@ -136,7 +136,7 @@ module cpu(clk, latclk, run, nreset, addr, rd, wr, data, 
                  .T(T), .N(N), .c(c),

                  .inst(inst[2:0]));

   wire `L incaddr, dataw, datas;

   wire tos2r, tos2n;

   wire tos2n;

   wire incby, bswap, addrsel, access, rd;

   wire [1:0] wr;